Embodiments of the present invention relate to a method for manufacturing a highly-integrated semiconductor device, and more particularly to a semiconductor device including a cell array where unit cells are vertically stacked in a multi-layered structure and a method for forming the semiconductor device.
A semiconductor memory device for use in a system comprised of several semiconductor devices has been used to store data therein. If a data processing device, e.g., a central processing unit (CPU), transmits a request of data, a semiconductor memory device outputs stored data corresponding to an address input from the data processing device, or stores data provided from the data processing device at a specific position corresponding to the address.
As the data storage capacity of the semiconductor memory device is increased, the size of a plurality of unit cells is gradually decreased, and the sizes of several constituent elements for read/write operations of data are also reduced. Therefore, assuming that there are no unnecessary overlapped wirings or transistors in the semiconductor memory device, it is important to minimize areas occupied by individual elements. In addition, reducing the size of unit cells contained in the semiconductor memory device is important to increase an integration degree of the semiconductor memory device.
A representative method for reducing production costs of the semiconductor memory device as well as increasing a profit of a manufacturing company is by increasing the integration degree of the semiconductor memory device. This is because the integration degree of the semiconductor memory device relates to how many chips can be formed on a single wafer. The semiconductor memory device includes a cell region including a plurality of unit cells, and the size of the cell region occupies a significant part of the entire size of the semiconductor memory device. The smaller the size of the unit cell, the smaller the entire size of the semiconductor memory device.
A general semiconductor memory device includes an 8F2- or 6F2-sized unit cell, wherein ‘F’ is a minimum line width or a minimum distance between patterns according to a specific design rule. According to the same design rule, the 6F2-sized unit cell is smaller than the 8F2-sized unit cell. As the semiconductor fabrication technology has been developed, F has been gradually reduced. However, the reduction of design rules is reaching the limit, and high costs are required to develop the fabrication technology for simplifying the design rule and products associated with the developed technology.
In recent times, a semiconductor memory device including a 4F2- or 2F2-sized unit cell has been proposed. The 2F2-sized unit cell is about two times smaller than the 4F2-sized unit cell, and is about four times smaller than the 8F2-sized unit cell. As a result, the semiconductor memory device including the 2F2-sized unit cell can be made in a smaller area even under the fabrication condition of the same design rule as those of other-sized semiconductor memory devices, and the competitiveness of the semiconductor memory device in international markets can be strengthened.